In semiconductor memory devices, data is read from or written to memory cells in the device according to decoded address information and various other control signals. Such memory devices are used for storage of data and/or program code in personal computer systems, embedded processor-based systems, video image processing circuits, communications devices, and the like. Ferroelectric memories store data in ferroelectric capacitors, and are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations. In a folded bitline 1T1C architecture, the individual ferroelectric memory cells typically include a ferroelectric (FE) capacitor adapted to store a binary data bit, together with a MOS access transistor, which operates to selectively connect the FE capacitor to one of a pair of complementary bitlines, with the other bitline being connected to a reference voltage for read operations. The individual cells are commonly organized as individual bits of a corresponding data word, where the cells of a given word are accessed concurrently by activation of platelines and wordlines by address decoding control circuitry.
Ferroelectric memory devices provide non-volatile data storage where the cell capacitors are constructed using ferroelectric dielectric material that may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the ferroelectric material. This alignment may be selectively achieved by application of an electric field that exceeds a coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. The response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a ferroelectric data cell is read by connecting a reference voltage to a first bitline and connecting the cell capacitor between a complementary bitline and a plateline signal. This provides a differential voltage on the bitline pair, which is connected to a differential sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between the voltage associated with a capacitor storing a binary “0” and that of the capacitor storing a binary “1”. The polarity of the sensed differential voltage thus represents the data stored in the cell, which is buffered by the sense amp and provided to a pair of local IO lines. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bitlines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry including address decoders and timing circuits in the device.
Connection of the ferroelectric cell capacitor between an activated plateline and the bitline during a read operation causes an electric field to be applied to the cell capacitor. If the field is applied in a direction to switch or reverse the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, the sense amplifier can measure the charge applied to the cell bitlines and produce either a logic “1” or “0” differential voltage at the sense amp terminals. Since reading the cell data is a destructive operation, the sensed data is then restored to the cell following each read operation by application of another pulse to the cell platelines while the sense amp is enabled. To write data to the cell, an electric field is applied to the cell capacitor by a sense amp or write buffer to polarize it to the desired state. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption.
Ferroelectric memory devices typically include a number of individually addressable memory cells arranged in an array configuration, wherein the array is typically organized as a matrix of rows and columns. Conventionally, data is stored into a memory array as a row, and read out from the memory array as a row, where the row typically consists of 8, 16, 32, or 64 bits of binary data. During a write operation, row decoder control circuitry provides a plateline pulse signal to the first sides of the ferroelectric cells in a data row, the other sides of which are connected to the array bitlines to receive the data. In a read operation, the decoder provides plateline pulses to the first side of each ferroelectric memory cell in a data row, and sense amplifiers are connected to the other side of the cells to sense a row of stored data bits in parallel fashion. Thus, in a single read operation, an entire row of data bits (e.g., 8, 16, 32, or 64 bits) are obtained from the memory cells in the selected row.
FIGS. 1A–1C illustrate a portion (e.g., a 32 k segment) of a ferroelectric memory device 2 organized in a folded bitline architecture, including a segment in FIG. 1A with 512 rows (words) and 64 columns (bits) of data storage cells 6 indicated as CROW-COLUMN, where each column of cells 6 is accessed via a pair of complementary bitlines BLCOLUMN and BLCOLUMN′. In the first row of the device 2, for example, the cells C1-1 through C1-64 form a 64 bit data word accessible via complementary bitline pairs BL1/BL1′ through BL64/BL64′ by activation of a wordline WL1. The cell data is sensed during data read operations using sense amp circuits 12 (S/A C1 through S/A C64) associated with columns 1 through 64, respectively. As illustrated further in FIG. 1B, an exemplary cell 6a is formed as a 1T1C cell including a single ferroelectric cell capacitor and an access transistor to connect the cell capacitor CFE1 and a MOS access transistor 10a between one of the complementary bitlines BL1 associated with the cell column and a plateline PL1. During memory accesses, the other bitline BL1′ is selectively connected to a reference voltage generator 8 or 8′ via one of a pair of switches 8a, 8b (FIG. 1A), depending upon which word is being accessed.
In the device 2, cells along WL1 and WL2 (as well as those along WL5, WL6, WL9, WL10, . . . , WL509, WL510) are coupled with bitlines BL1–BL64, whereas cells along WL3 and WL4 (as well as those along WL7, WL8, WL11, WL12, . . . , WL511, WL512) are coupled with bitlines BL1′–BL64′. In reading the first data word along the wordline WL1, the cells C1-1 through C1-64 are connected to the sense amps via the bitlines BL1, BL2 . . . , BL63, and BL64 while the complementary reference bitlines BL1′, BL2′ . . . , BL63′, and BL64′ are connected to the reference voltage generators 8, 8′. FIG. 1C provides a timing diagram 20 showing waveforms or signals on various nodes during a read and restore operation in the device 2 to access cells along WL1.
During a read operation, a signal level V1 or V0 is obtained on the array bitline BL1, depending upon the state of the data being read from the cell 6a (e.g., binary “1” or “0”, respectively). A reference voltage VREF from the shared reference generators 8, 8′ is ideally between V1 and V0, which is then applied to the complementary bitline BL1′ (e.g., the other input of the sense amp 12). To read the data stored in the cell, the transistor 10a is turned on by applying a voltage Vwl which is typically greater or equal to Vdd plus the threshold voltage of the transistor 10a via the wordline WL1 to couple the bitline BL1 to the capacitor CFE1. The plateline PL1 is then pulsed high, as illustrated in FIG. 1C, to cause charge sharing between the ferroelectric capacitor CFE1 and the capacitance of the bitline BL1, by which the bitline voltage BL1 rises, depending upon the state of the cell data being read. The plateline PL1 is then returned to 0V and the sense amp 12 is activated via an enable signal SE. One input terminal of the sense amp 12 is coupled to the cell bitline (e.g., data bitline BL1) and the other differential sense amp input is coupled to a reference voltage (e.g., reference bitline BL1′ in this example). In the example of FIGS. 1A–1C, the sense amp 12 is enabled after the plateline signal PL1 is again brought low, a technique referred to as “pulse sensing”. Alternatively, “step sensing” can be used in the device 2, in which the sense amp is enabled via the SE signal while the plateline pulse PL1 is still high. Following a cell data read, the data is restored to the cell 6a by again pulsing the plateline high and then low while the wordline WL1 is asserted to reprogram the cell capacitor CFE1.
Recently, ferroelectric memory devices have been proposed, in which several adjacent cell platelines are connected to a single common plateline driver in a segment, in order to conserve driver area in the device. These groups of cells form a plate group, for example, where a memory array segment of 512 rows (e.g., 512 wordlines) may have cells along wordlines WL1 through WL64 driven by a single plateline driver, with other portions of the segment forming separate plate groups of 64 rows each. Also, wordline driver circuit area may be conserved by providing common wordline drivers shared among several or all segments in a section within a memory device. For example, a 6M FeRAM may consists of 12 sections (1 through 12) and each section may have 16 segments (1 through 16) of 32K memory arrays. In a shared plateline driver configuration, accessing a selected target row in an array segment may cause unwanted charging or discharging of storage nodes associated with unselected cells within the plate group, typically by current leakage of the unselected cell transistor. Other sources of unwanted storage node charging or discharging occur in non-shared plateline configurations as well. Such unintended charge transfer can degrade signal margins required to accurately and repeatably sense the data stored in ferroelectric memory cells.
In reference to FIG. 1B, the storage node of the cell 6a is the connection between the cell capacitor CFE1 and the cell transistor 10a. Where the selected cell 6a is read (e.g., along with other cells 6 along WL1), pulsing the plateline PL1 high causes a voltage to develop on the bitline BL1 because the cell capacitor CFE1 discharges through the pass gate transistor 10a to the bitline BL1. Once the bitline signal is amplified by the sense amp 12 during a write or restore operation, the bitline goes high to Vdd or low to Vss, depending on whether the data being written is a binary “1” or a “0”, respectively. Where the cell 6a is not selected for a read or write access (e.g., WL1 is low and transistor 10a is theoretically off), a pulse to the plateline PL1 in a shared plate line device causes the voltage at the storage node to increase, typically to a voltage near the plateline pulse voltage which is typically Vdd or higher. If the cell transistor 10a leaks (e.g., sub-threshold conduction or other transistor leakage mechanism) and the bitline BL1 is at a lower voltage than the plateline (e.g., where a data “0” is being read or written to another cell along BL1), the storage node can loose charge to the bitline BL1. The non-accessed cell 6a can also acquire charge while the plateline PL1 is low, for example, where the data on the bitline BL1 is a “1” (e.g., BL1 is at a high voltage such as Vdd), due to leakage through the cell transistor 10a. 
These charge loss and gain disturbances can accumulate over a number of cycles, thereby decreasing the signal margin of the system, and possibly depolarizing the cell capacitor CFE1 from its intended (e.g., programmed) state. Furthermore, such storage node disturbances may be worsened through wordline coupling that temporarily raises the wordline voltage WL1 while a different row is being accessed. Consequently, there is a need for improved ferroelectric memory devices and techniques by which cell storage node disturbances can be mitigated or avoided.